Tinymembench Result For Ci20
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 112.4 MB/s (1.1%)
C copy backwards (32 byte blocks) : 112.7 MB/s
C copy backwards (64 byte blocks) : 112.6 MB/s
C copy : 113.9 MB/s
C copy prefetched (32 bytes step) : 113.9 MB/s
C copy prefetched (64 bytes step) : 114.0 MB/s (0.1%)
C 2-pass copy : 171.1 MB/s
C 2-pass copy prefetched (32 bytes step) : 171.1 MB/s (0.3%)
C 2-pass copy prefetched (64 bytes step) : 170.9 MB/s
C fill : 378.3 MB/s (1.1%)
C fill (shuffle within 16 byte blocks) : 378.4 MB/s (0.2%)
C fill (shuffle within 32 byte blocks) : 375.4 MB/s
C fill (shuffle within 64 byte blocks) : 378.7 MB/s (0.6%)
---
standard memcpy : 113.1 MB/s
standard memset : 378.7 MB/s (0.6%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.3 ns / 0.4 ns
65536 : 12.0 ns / 25.7 ns
131072 : 18.1 ns / 41.3 ns
262144 : 24.8 ns / 59.5 ns
524288 : 69.0 ns / 144.9 ns
1048576 : 259.6 ns / 526.1 ns
2097152 : 314.3 ns / 634.3 ns
4194304 : 332.4 ns / 670.8 ns
8388608 : 340.1 ns / 689.6 ns
16777216 : 346.3 ns / 712.7 ns
33554432 : 353.8 ns / 729.3 ns
67108864 : 361.0 ns / 742.7 ns
page revision: 0, last edited: 25 Jun 2017 19:07