The ROP2 compiler is based on the MIPS OP2 compiler. Front end modules (ROPM.Mod ROPS.Mod ROPT.Mod ROPB.Mod ROPP.Mod) start with an "R" and are nearly the same as the MIPS version. Back end Modules ( AOPL.Mod AOPC.Mod AOPV.Mod, MOPL.Mod MOPC.Mod MOPV.Mod resp. VOPL.Mod VOPC.Mod VOPV.Mod) start with A for ARMv7, M for MIPS and V for RISC-V. Compiler module is named ROP2.Mod, resulting in RCompiler.Obj object file. Compiling commands are RCompiler.CompileA, RCompiler.CompileM resp. RCompiler.CompileV.
Main differences between MIPS and RISC-V:
- RISC-V has PC relative instruction via AUIPC while MIPS has not
- some instructions like shift immediate are encoded differently
- RISC-V does not have a branch delay slot while MIPS has
- LUI is 20 bit for RISC-V and 16 bit for MIPS. This causes branch, immediate arithmetic, load/store on RISC-V having only 12 bit for the immediate value
- PC is advanced by 4 on MIPS
RISC-V also seems to be quite similar to ARMv8. Once RISC-V code generation works, adding ARMv8 should be very easy.
The project of writing an RISC-V compiler and porting the system started about in March 2016. Beginning of October 2016 the compiler has no obvious bugs and the system including Gadgets starts. This took about half a year.
Writing a RISC-V backend is quite easy. As RISC-V hardware is only just emerging, most people likely will use Qemu. RISC-V kernel is not mainlined yet for good reasons. This means that the kernel can and will change in incompatible ways.
Instructions to use RISC-V version with qemu
- get qemu from [https://github.com/arsv/riscv-qemu] and make riscv32-linux-user target
- from within olx compile OLR.MBootLinker.Mod
- compile gadgets on x86 (fast) or later within qemu (slow)
- start qemu via "qemu-riscv32 olv"