Current (since olr151219.tgz) release ships with good old Hennessy3.pm.Mod benchmark suite. Here are the results for MIPS ci20, ARM Cortex A7 Orange Pi PC and Cortex A53 Orange Pi PC2 computers, all running at 1.2/1.3 GHz. No results of original MIPS compiler as old olr versions don't run on current ci20 Debian. Dim3 is the graphics benchmark of Dim3.Panel in Gadgets.
RPi3 was benchmarked using old version of Ceres based compiler which is about 10% slower than new version.
| M1s BL808 | MIPS ci20 | OPi PC, POA | OPi PC2, POA | RPi 4, POA | OPi PC, Ceres compiler | OPi PC, ROP2 compiler | OPi PC, ROP2.170618 | RPi 3, old Ceres compiler | Haswell @ 3.2GHz | Haswell @ 1.2GHz | oberonc Intel n100 1st run..11th run | |
| Perm | 82 | 23 | 28 | 23 | 9 | 31 | 30 | 24 | 28 | 4 | 9 | 28..2 |
| Towers | 121 | 40 | 32 | 27 | 8 | 34 | 39 | 33 | 33 | 3 | 9 | 9..2 |
| Queens | 62 | 22 | 20 | 18 | 8 | 22 | 23 | 20 | 22 | 2 | 5 | 9..3 |
| Intmm | 91 | 28 | 26 | 20 | 8 | 30 | 29 | 17 | 27 | 2 | 7 | 12..1 |
| Mm | 88 | 36 | 26 | 21 | 8 | 33 | 30 | 19 | 31 | 3 | 7 | 13..1 |
| Puzzle | 712 | 213 | 199 | 177 | 60 | 210 | 240 | 171 | 206 | 26 | 77 | 36..12 |
| Quick | 71 | 20 | 20 | 18 | 12 | 28 | 27 | 19 | 28 | 6 | 16 | 17..5 |
| Bubble | 186 | 50 | 47 | 41 | 16 | 57 | 55 | 38 | 59 | 7 | 14 | 17..4 |
| Tree | 68 | 27 | 22 | 18 | 13 | 29 | 25 | 21 | 28 | 7..21 | 37 | 22..3 |
| FFT | 155 | 55 | 36 | 30 | 13 | 60 | 55 | 39 | 60 | 7 | 32 | 17..2 |
| NonFP: | ?? | 510 | 470 | 397 | 172 | 539 | 553 | 418 | 529 | 71.3 | 242 | 237..45 |
| FP: | ?? | 859 | 703 | 596 | 249 | 902 | 885 | 647 | 886 | 114 | 367 | 350..56 |
| Dim3 | 1.34s | N/A | N/A | N/A | 1.04s | 0.95s | 0.77s | 0.14s | 0.43s |
Tree allocates lots of small chunks of memory on the heap. Performance depends on heap state.
MIPS ci20 gets its performance from register variables and passing parameters via registers while memory interface is slow.
ARM ceres compiler has neither register variables nor passing parameters via registers but sophisticated addressing modes.
ARM ROP2 compiler only using basic addressing modes but register variables. No parameter passing via registers. Cortex A7 is an impressive hardware implementation of a mediocre instruction set.
X86 is very fast hardware with very complex instruction set not well suited for Oberon.
POA currrently does not run well on RPi4 supposedly due to slow X11 implementation of used functions.